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full - feature ? 48 v hot swap controller data sheet adm1073 rev. b document feedback information furnished by analog devices is believed to be accu rate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is grant ed by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2 004 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features precision inrush linear current limit soft start inrush current limit profiling precision maximum on - time in current limit maximum on - time modulated by fet drain voltage for additional soa protection adjustable pwm retry scheme and multiple device cascading capability for charging large capacitive loads limited number of pwm cycles for fet soa protection under short circuit condition ability to configure device a s continuous autoretry with a 5 - s econd cooling period shunt regulator topology to allow very large transient input supplies separate uv and ov pins for programming allowable input supply window programmable ov hysteresis using current source into pin when supply is high programmable uv hysteresis using current sink from pin when supply is lo w pwrgd output indicates w hen capacitor charging complete splygd output indicates when supply is within valid window latched output indicates the end of the retry cycle before load capac itance is charged shdn input for user - commanded shutdown restart input for user - triggered 5 - second shutdown and autorestart virtual card res eat functional block diagram 04488-001 f au l t timer and contro l oscill a t or pwm timeout foldback and pwrgd 5 second shutdown t on contro l soft s t art contro l unde r vo lt age detec t or ove r vo lt age detec t or v cc and reference gener a t or l a tched res t art sp l ygd v in ov uv ss timer shdn v ee sense g a te drain pwrgd 100mv(max) 50 a v in figure 1. applications central office switching telecommunication and data communication equipm ent ?48 v distributed power systems negative power supply control high availability servers ?48 v power supply modules disk arrays general description the adm1073 is a full - feature, negative voltage, hot swap controller that allows boards to be safely insert ed and removed from a live ?48 v backplane. the part provides precise and robust current limiting, and protection against both transient and nontransient short circuits in overvoltage and undervoltage conditions. the adm1073 can operate from a negative vol tage of ?18 v to ?80 v and can tolerate transient voltages of up to ?200 v. inrush current is limited to a programmable value by control - ling the gate drive of an external n - channel fet. the maximum current limit is set by the choice of the sense resistor, r sense . a built - in soft start function allows control of the inrush current profile by an external capacitor on the soft start (ss) pin. an external capacitor on the timer pin determines the time for which the fet gate is controlled to be high when maxi mum inrush current flows. the adm1073 employs a limited consec - u tive retry scheme, whereby, if the load capacitance is not fully charged within one attempt, the fet gate is pulled low and retries after a cooling period. (continued on page 3 )
adm1073 data sheet rev. b | page 2 of 24 table of contents general description ......................................................................... 3 specifications ..................................................................................... 4 absolute maximum ratings ............................................................ 6 thermal characteristics .............................................................. 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 functional description .................................................................. 13 hot circuit insertion ................................................................. 13 initial startup .............................................................................. 13 board removal ........................................................................... 14 controlling the current ............................................................. 14 sense ............................................................................................. 15 sense resistor .............................................................................. 15 soft start (ss pin) ....................................................................... 15 gate ............................................................................................ 15 v in ................................................................................................. 15 v ee ................................................................................................. 15 timing control timer ......................................................... 15 drain ............................................................................................ 16 pwrgd ....................................................................................... 16 latched ................................................................................... 16 splygd ....................................................................................... 16 restart ..................................................................................... 16 shdn ........................................................................................... 16 undervoltage/overvoltage detection ..................................... 16 functionality and timing .............................................................. 18 live insertion .............................................................................. 18 overvoltage and undervoltage faults ..................................... 18 soft start ...................................................................................... 19 current faults ............................................................................. 20 logic inputs ................................................................................. 21 kelvin sense resistor connection ........................................... 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision histo ry 7 / 13 rev. a to rev. b changes to figure 15 ...................................................................... 10 changes to figure 32 ...................................................................... 13 changes to v ov equation .............................................................. 17 2 / 12 rev. 0 to rev. a updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 4 / 04 revision 0: initial version
data sheet adm1073 rev. b | page 3 of 24 general description (continued from p age 1) further control of the inrush current is provided by modulating the width of the pulses, depending on the drain - source voltage across the fet . this allows maximum charge transfer to the load capacitance while maintaining the fet in its safe operating area (soa). the default duty cycle of the pulse train is 6%, decreasing to 2.5% with maximum fet drain - source voltage, with a maximum of seven successive autorestarts. after seven successive autorestarts, the fault is latched and the part goes into shutdo wn, with the result that the external fet is disabled until the power is reset. the latched output signal indicates when the seven retries are complete. further programmability is offered by allowing alteration of the default 6% rat io. an extra resist or between the timer pin and v ee allows the ratio of on - time to off - time to be decreased, while a resistor between timer and v in allows the ratio to be increased. the adm1073 has separate uv and ov pins for undervoltage and overvoltage d etection. the fet is turned off, if a nontransient voltage less than the undervoltage threshold ( typically ?36 v) is detected on the uv pin, or if greater than the overvoltage threshold (typically ?80 v) is detected on the ov pin. the operating voltage window of the adm1073 is programma ble via resistor networks on the uv and ov pins. the hysteresis levels on the undervoltage and overvoltage detectors can also be altered (see the undervoltage/overvoltage detection section). the splygd output signal indicates when the backplane supply is within the exter nally programmable operating voltage range. other functions include ? pwrgd output, which can be used to enable a power module (the drain pin is monitored to determine when the load capacitance is fully charged) ? shd n input to manually disable the gate drive ? restart input to remotely initiate a 5 second shutdown the adm1073 is fabricated using bicmos technology for minimal power consumption and is available in a 14 - lead tssop package.
adm1073 data sheet rev. b | page 4 of 24 specifications v dd = 0 v, v ee = ?48 v; t a = ?40c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions board supply (not connected directly to device) limited by external components maximum voltage range ?200 ?48 ?18 v typical operating voltage range ?80 ?48 ?35 v v in pinshunt regulator operating supply voltage range 11.7 12.3 12.9 v i in = 0.6 ma to 2 ma quiescent supply current 300 500 a v in = 11.7 v maximum shunt supply voltage 14 v i in = 10 ma undervoltage lockout, v lko 8 v power-on reset delay 150 ms uv, ov pinsundervoltage and overvoltage detection undervoltage falling threshold, v uvf 825 868 910 mv undervoltage hysteresis current 5 a undervoltage fault filter 0.6 ms overvoltage rising threshold, v ovr 1.86 1.93 2.00 v overvoltage hysteresis current 5 a overvoltage fault filter 5 s input current 0.2 a gate pinfet driver maximum gate voltage 11.5 v in(max) v i gate = ?1.0 a minimum gate voltage 10 100 mv i gate = 1.0 a pull-up current ?50 a v gate = 0 v to 8 v; v ss = 2 v ?36 a v gate = 0 v to 8 v; v ss = 0 v pull-down current 20 ma v gate > 2 v 50 ma v gate > 5 v sense pincurrent sensesoft start current limit control loop threshold, v acl 97 100 103 mv i gate = 0 ma circuit breaker limit voltage, v cb 86 90 mv fast current limit voltage, v fcl 110 mv control loop transconductance 4.5 a/mv soft start pin current 5 a timer pinpwm control minimum timer pull-up current 18 19 20 a i pwrgd < 4 a; t a = 25c to 85c 16 19 20 a i pwrgd < 4 a maximum timer pull-up current 37 39 41 a i pwrgd = 24 a; t a = 25c to 85c 34 39 41 a i pwrgd = 24 a timer pull-down current 1 a timer low voltage trip point 0.45 0.50 0.55 v timer high voltage trip point 2.34 2.42 2.50 v current limit on-time, t on 6 ms i drain = 4 a; c timer = 47 nf current limit on-time, t on , with foldback 3 ms i drain = 20 a; c timer = 47 nf number of consecutive pwm retry cycles 7 continuous short-circuit time befo re latched shutdown 0.6 s c timer = 47 nf
data sheet adm1073 rev. b | page 5 of 24 parameter min typ max unit test conditions drain (foldback) and pwrgd drain voltage at which pwrgd asserts 1.9 2 2.1 v r drain = 3.75 m to 20 m maximum drain pin current allow abl e , i drain(max) 36 a v ds = 80 v; r drain = 3.25 m pwrgd output voltage low 1 2 v i pwrgd = 2.5 ma 0.2 0.4 v i pwrgd = 0.5 ma pwrgd internal pull - up current 6 a pwrgd output voltage high v in v rest art time before restart 5 s input threshold 1.35 1.45 1.55 v glitch filter 5 s internal pull - up current 6 a shdn glitch filter 5 s input threshold 1.35 1.45 1.55 v internal pull - up current 6 a latched and splygd output voltage low 1 2 v i latched , i splygd = 2.5 ma 0.2 0.4 v i latched , i splygd = 0.5 ma internal pull - up current 6 a output voltage high v in v
adm1073 data sheet rev. b | page 6 of 24 absolute maximum rat ings all voltages referred to v ee , t a = 25c, unless otherwise noted. table 2 . parameter rating supply voltage (v dd ? v ee ) ?0.3 v to ?200.0 v maximum shunt supply voltage, v ss 16 v sense pin ?2 v to +2 v gate pin ?0.3 v to +16 v uv pin ?0.3 v to +6 v ov pin ?0.3 v to +6 v ss pin ?0.3 v to +6 v timer pin ?0.3 v to +6 v drain pin ?0.3 v to +6 v shdn p in ?0.3 v to +16 v splygd pin ?0.3 v to +16 v latched pin ?0.3 v to +16 v pwrgd pin ?0.3 v to +16 v restart pin ?0.3 v to +16 v maximum junction temperature 12 5c operating temperature range ?40c to +85c continuous power dissipation 180 mw storage temperature range ?65c to +150c lead temperature (soldering, 10 s) 300c stresses above those listed under absolute maximum ratings may cause permanent dama ge to the device. this is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characterist ics 14- lead tssop package: ja = 240c/w jc = 43c/w esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features pro prietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
data sheet adm1073 rev. b | page 7 of 24 pin configurati on and function desc riptions adm1073 t o p view (not to scale) res t art 1 v in 2 pwrgd 3 ss 4 sense 5 shdn timer uv ov drain 14 13 12 1 1 10 v ee 6 l a tched 7 g a te sp l ygd 9 8 04488-002 figure 2 . pin configuration table 3 . pin function descriptions pin number mnemonic function 1 restart input p in. edge - triggered 5 - second shutdown a nd automatic restart. 2 v in shunt regulated positive supply to chip. connect to the positive supply rail via shunt resistor. a 1 f capacitor to v ee is recommended on the v in pin. 3 pwrgd open drain output. signals that the hot sw ap is complete. 4 ss analog pin for soft start . an external capacitor on this pin sets the ramp rate of the inrush current profile. this pin can be overdriven to alter the current limit control loop threshold. 5 sense voltage input from external sens e resistor. 6 v ee ground supply to chip (usually a ? 48 v system supply). also low - side sense resistor connection. 7 latched open drain output. signals the end of the pwm retry period after a current fault. 8 splygd open drain output. signals that the device is not in reset and that the supply is in operating voltage window. 9 gate output to external fet gate drive. 10 drain analog input for monitoring of fet drain voltage. 11 ov input pin for overvol tage detection circuitry. 12 uv input pin for undervoltage detection circuitry. 13 timer analog pin. an external capacitor on this pin sets the maximum allowable time in current limit, the pwm on - time , and the pwm duty cycle. 14 shdn input p in. level - triggered device shutdown and reset.
adm1073 data sheet rev. b | page 8 of 24 typical performance characteristics 04488-003 temperature (c) 85 ?50?35?20?51025405570 i in ( ? a) 0 500 450 400 350 300 250 200 150 100 50 figure 3. i in vs. temperature 04488-004 v in (v) 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 i in (ma) 0.1 100.0 10.0 1.0 t a = +85c t a = +25c t a = ?40c figure 4. i in vs. v in 04488-005 temperature (c) 85 ?50 ?35 ?20 ?5 10 25 40 55 70 r z ( ) 0 10 7 8 9 3 4 5 6 1 2 figure 5. r z (v in forward voltage) vs. temperature 04488-006 temperature (c) 85 ?50 ?35 ?20 ?5 10 25 40 55 70 v in (v) 11.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 figure 6. v in vs. temperature 04488-007 temperature (c) 85 ?50 ?35 ?20 ?5 ?10 25 40 55 70 v lko (v) 0 12 8 10 4 6 2 figure 7. undervoltage lockout, v lko , vs. temperature 04488-008 temperature (c) 85 ?50 ?35 ?20 ?50 10 25 40 55 70 delay (ms) 0 400 250 300 350 150 200 100 50 figure 8. por delay vs. temperature
data sheet adm1073 rev. b | page 9 of 24 04488-009 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 v g a te l (mv) 0 10 100 70 80 90 30 40 50 60 20 figure 9. v gatel vs. temperature 04488-010 temper a ture ( c) 85 ?50 ? 35 ?20 ? 5 10 25 40 55 70 v g a teh ( v ) 10.0 10.5 14.0 12.5 13.0 13.5 1 1.0 1 1.5 12.0 figure 10 . v gateh vs. temperature 04488-0 1 1 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 i g a te ( a) 0 100 90 80 70 60 50 40 30 20 10 ss = 2v ss = 0v figure 11 . i gate (source) vs. temperature 04488-012 v g a te (v) 12.0 8.0 8.5 9.0 9.5 10.0 10.5 1 1.0 1 1.5 i g a te (ma) 0 50 30 35 40 45 15 20 25 5 10 ss = 0v ss = 2v figure 12 . i gate (source) vs. v gate 04488-013 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 i g a te (ma) 0 60 40 30 50 20 10 figure 13 . i gate (fcl, sink) vs. temperature (v gate = 2 v) 04488-014 v g a te (v) 12 1 2 3 4 5 6 7 8 9 10 1 1 i g a te (ma) 0 100 90 80 60 70 30 40 50 20 10 figure 14 . i gate (fcl, sink) vs. v gate
adm1073 data sheet rev. b | page 10 of 24 04488-015 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 v uv (mv) 800 1000 980 960 920 900 880 940 860 840 820 figure 15 . uv threshold vs. temperature 04488-016 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 50 10 25 40 55 70 v ov (v) 1.80 1.82 2.00 1.92 1.94 1.96 1.98 1.84 1.86 1.88 1.90 figure 16 . ov threshold vs. temperature 04488-017 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 del a y (ms) 0 2.0 1.2 1.4 1.6 1.8 0.8 1.0 0.6 0.2 0.4 figure 17 . uv voltage fault filter time vs. temperature 04488-018 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 del a y ( s) 0 10 7 6 5 4 9 8 3 2 1 figure 18 . ov voltage fault filter time vs. temperature 04488-019 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 i sense ( a) 0 0.5 1.0 5.0 3.5 4.0 4.5 1.5 2.0 2.5 3.0 figure 19 . i sense vs. temperature (v sense = 50 mv) 04488-020 v sense (v) 2.0 ? 2 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 1.5 i sense ( a) ? 80 ? 60 ? 40 80 20 40 60 0 ? 20 figure 20 . i sense vs. (v sense ? v ee )
data sheet adm1073 rev. b | page 11 of 24 04488-021 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 v (mv) 80 85 90 120 105 1 10 1 15 95 100 v fc l v ac l v cb figure 21 . voltage limits for load current control vs. temperature 04488-022 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 timer threshold (v) 0 0.5 3.0 2.0 2.5 1.0 1.5 v tmr (low) v tmr (high) figure 22 . high and low timer thresholds vs. temperature 04488-023 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 timer (ms) 0 2 4 20 12 14 16 18 6 8 10 figure 23 . maximum current limit o n - time vs. temperature (i drain = 4 a, c timer = 47 nf) 04488-024 c timer (nf) 100 0 30 20 10 40 50 60 70 80 90 1.0nf 4.7nf 10.0nf 22.0nf 33.0nf 47.0nf 68.0nf 82.0nf 100.0nf timer ( ms) 0 12 10 8 6 4 2 14 figure 24 . current limit on - time vs. c timer (1 nf ? 100 nf) 04488-025 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 pwm (%) 0 10 9 8 7 6 5 4 3 2 1 figure 25 . current limit pwm vs. temperature 04488-026 r timer (m ? ) 10 0 1 2 3 4 5 6 7 8 9 pwm (%) 0 5 10 50 30 35 40 45 15 20 25 figure 26 . current limit pwm vs. r timer
adm1073 data sheet rev. b | page 12 of 24 04488-027 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 t short (s) 0 0.1 0.2 1.0 0.6 0.7 0.8 0.9 0.3 0.4 0.5 figure 27 . continuous short circuit time before shutdown vs. temperature 04488-028 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 t res t art (s) 0 1 2 10 6 7 8 9 4 5 3 figure 28 . restart time vs. temperature 04488-029 c ss (nf) 10 0 1 2 3 4 5 6 7 8 9 t ram p (ms) 0 0.5 1.0 5.0 3.5 4.0 4.5 1.5 2.0 2.5 3.0 1.0nf 1.5nf 2.2nf 3.3nf 4.7nf 6.8nf 10.0nf figure 29 . soft start ramp time vs. c ss 04488-030 temper a ture ( c) 85 ? 50 ? 35 ? 20 ? 5 10 25 40 55 70 i uv/ov (a) 0 1 2 10 6 7 8 9 3 4 5 figure 30 . i uv / ov vs. temperature
data sheet adm1073 rev. b | page 13 of 24 functional descripti on hot circuit insertio n inserting circuit boards into a live ?48 v backplane can cause large transient currents to be drawn as the board capacitance charges up. these transient currents can cause glitches on the system power supply and can permanently damage the board connectors and components. the adm1073 i s designed to control the manner in which a boards supply voltage is applied so that harmful transient currents do not occur and the board can be safely inserted or removed from a live backplane. undervoltage, overvoltage, and overcurrent protection are o ther features of the part. the adm1073 ensures that the input voltage is stable and within tolerance before being applied to the power module. initial startup the adm1073 hot swap controller normally resides on a removable circuit board and controls the manner in which power is applied to the board upon conne ction. this is achieved using a fet, q1, in the power path (see figure 31 ). by controlling the gate voltage of the transistor, the surge of current to charge load capacitance can be limited to a safe value when the board makes connection. the adm1073 can also reside on the backplane itself and perform the same function from there. figure 32 shows a typical adm1073 application circuit. when the plug - in board is inserted into the live backplane, the ?48 v and 0 v lines connect to the live supply. this powers up the device with the voltage on v in exceeding v lko . when the voltage on the uv pin exceeds the undervoltage rising threshold (0.868 v), it is now inside the programmed operating voltage window. it must stay inside this window for the duration of the power - on reset delay time, t por (150 ms). shdn res t art r dro p r drain l a tched sp l ygd pwrgd adm1073 c timer c ss c load r4 r3 r2 r1 dc-dc converter v in + v in ? 04488-031 r sense fet live backplane 0v ?48v plug-in board figure 31 . adm1073 topology f au l t timer and contro l oscill a t or pwm timeout foldback and pwrgd 5 second shutdown timer contro l soft s t art contro l unde r vo lt age detec t or ove r vo lt age detec t or v cc and reference gener a t or l a tched res t art sp l ygd v in ov uv ss timer shdn v ee sense g a te drain r drain pwrgd 100mv(max) 50 a v in fet r sense r dro p dc-dc converter 5v 3.3v 2.8v ...etc. gnd r 1 r 2 r timer * c timer r 3 r 4 c ss ? 48v rtn ?48v 04488-032 v ee *r timer is an optiona l component figure 32 . adm1073 applicat ion diagram
adm1073 data sheet rev. b | page 14 of 24 when the device detects that the supply voltage is valid, it ramps up the gate voltage until the fet turns on and the load current increases. the adm1073 monitors the level of the current flowing through the fet by sensing the voltage across the external sense resistor, r sense . when the sense voltage reaches 100 mv, the gate pin is actively controlled, limiting the load current. in this way, the maximum current permitted to flow through the load is set by the choice of r sense . if a change in the level of the supply voltage causes the voltage on uv to fall below the undervoltage falling threshold (v uvf ), or the voltage on ov to rise above the overvoltage rising threshold (v ovr ), then the gate drive is disabled. board removal if the board is rem oved from a card cage, the voltage on the uv pin falls to zero (that is, outside operating range) and the gate drive is de - asserted, turning off the fet. controlling the curr ent the adm1073 features the following current control functions: ? precision maximu m current limit ? controlled time in current limit ? limited number of consecutive maximum current events ? current limit profiling soft sta rt ? overcurrent fast limit in the following sections, five distinct system operating conditions are described with referenc e to the current control features. startup into nominal load capacitance once the supply voltage has exceeded the uv threshold, and following the 0.6 ms uv filter time, the current to the load ramps up linearly as the capacitor on the soft start (ss) pin i s charged to 2.5 v. at the same time, current is sourced into the cap acitor on the timer pin, both from an on - chip source and via the drain resistor. once the soft start voltage has reached 2.5 v, the current to the load is limited to i max ( 100 mv/r sense ). assuming that the values of r sense and the timer capacitance have been chosen to allow the load capacitance to charge within one on period (t on period), the load cap acitor is fully charged before the voltage on timer reaches 2.5 v. at this point, the curr ent to the load decreases, and the fet gate voltage increases to v ss , connecting the supply to the load. startup into load with large capacitance if the load capacitance is sufficiently large that to charge it fully in one attempt would compromise the fet s soa, consecutive maximum current events may be used. the use of this tech - nique assumes that the load is not yet enabled, so negligible load current is demanded. the initial current profiling is identical to that for startup into a nominal load capacitan ce. if the charge passed to the load in time t on with maximum current flowing is insufficient to fully charge the load capacitance, at the end of the t on period the load capacitance is still demand ing maximum current. the adm1073 now controls the fet gate to zero for a time t off , determined by the time taken for the on - chip current sink to discharge the timer capacitance to 0.5 v. at the end of time t off , the device retries, again following the soft star t current profile. in this way, a large load capaci t ance can be charged using consecutive current limit periods. the external compo nents should be chosen to ensure that the capacitance is fully char ged within seven timer periods, if the default limited consecutive retry mode is used . startup into a short c ircuit or over current fault the load might demand large currents at initial connection. the adm1073 follows the soft start current profile as described for startup into a nominal load. the current is limited at i max for time t on following which the fet ga te is pulled low. the fet gate is held low for time t off , before retrying, again with the soft start current profile. the adm1073 cycles through 7 retries, afte r which it latches the fet off, assuming the default limited consecutive r etry mode is used . vol tage step during normal operation once the load capacitance is charged at initial board insertion and a pwrgd signal is issued by the adm1073, the load begins to demand current. therefore, following a step increase in the magnitude o f the supply voltage, not all the fet current is available for charging of the load capacitance. because the fet is fully on following a step in the supply voltage, the current increases immediately from i load to supply charge to the load capacitance. if t he current remains below the fast current limit, the fet gate drive amplifier controls it back to i max . if the current exceeds the fast current limit, the fet gate is strongly pulled down and back into regulation with the current at i max . the size of the v oltage step and the headroom between the load current and i max determine the time required at i max to charge the load capacitance. external components should be chosen to ensure that any expected step size leads to a requirement of less than time t on to ch arge the load capacitance. short circuit or overcurrent fault during operation if a short circuit or an overcurrent fault occurs during normal operation, the fet is fully on and initially allows increased current to flow. if the current remains below the f ast current limit, the fet gate drive amplifier controls it back to i max . if the current exceeds the fast current limit, the fet gate is strongly pulled down and back into regulation with the current at i max . following a period , t on , the adm1073 pulls the fet gate low for a time t off , then retries following the soft start current profile. if the fault persists, the adm1073 cycles through 7 retries before latching off. if the fault clears within the 7 - retry period, the adm1073 controls the fet gate high to a llow normal operation to continue.
data sheet adm1073 rev. b | page 15 of 24 sense the sense pin is used for sensing the voltage across an external power sense resistor. this voltage is differentially measured with respect to v ee , and used to control the gate. if sense is lower than 100 mv (after the soft start time), the gate pin is allowed to increase up to 12 v to provide maximum fet enhancement. if the current increases such that the sense pin tries to go above 100 mv, the gate pin is controlled in a feedback loop to ensure that the voltage ac ross the sense resistor is regulated at exactly 100 mv. sense resistor the adm1073s current limiting function can operate at different current levels. the current limit is determined by selection of the sense resistor, r sense . ta ble 4 shows how the maximum allowable load current (i load(max) ) and the minimum and maximum inrush currents (i limit(min) and i limit(max) ) are related to the value of r sense . table 4 . minumum and maximum inrush current and load curr ent levels for different values of r sense r sense (m?) i load(max) (a) i limit(min) (a) i limit(max) (a) 5 17.20 19.40 20.60 10 8.60 9.70 10.30 15 5.73 6.47 6.87 18 4.78 5.39 5.72 22 3.91 4.41 4.68 33 2.61 2.94 3.12 47 1.83 2.06 2.19 51 1.69 1.90 2.02 68 1.26 1.43 1.51 75 1.15 1.29 1.3 7 90 0.96 1.08 1.14 soft start (ss pin) the ss pin is used to determine the inrush current profile. a capacitor should be attached to this pin. whenever the fet is requested to turn on, the ss pin is held at ground until the sense pin reaches a few mv . a current source is then turned on, which linearly ramps the capacitor up to 2.5 v. the reference voltage for the gate linear control amplifier is derived from the soft start voltage, such that the inrush linear current limit is defined as sense start soft limit r v i = 20 / _ overdriving the ss pin the ss pin can be overdriven externally from 0.360 v to 1.95 v to offset the current limit control loop threshold from 18 mv to 100 mv. this allows different current limits to be selected at different points of operation w ithout using multiple sense resistors. the current limit voltage is clamped at 100 mv maximum. gate analog output for driving the external fet gate. this pin is switched to v ee when the fet is off, is linearly controlled when the fet is at the programmed i nrush current limit, and is switched to v in when the fet is fully enhanced. the source current capability is small to provide slow controlled turn - on, and the sink current capability is large to provide fast turn - off. v in positive supply pin. this current - driven supply is shunt - regulated at 12.3 v internally, and should be connected to the most positive input supply terminal (usually ?48 v rtn or 0 v) through a dropper resistor. the resistor should be chosen such that it always supplies enough current to overcome the maximum quiescent supply current of the chip. default r drop = 30 k ? . v ee negative supply input. this pin should be conne cted directly to the most negative input supply terminal (?48 v). this pin is also used for differentially sensing across the external power resistor, and should, therefore, be connected as close to the sense resistor as possible. (see the kelvin sense resistor connection section.) timing control timer the timer pin is an analog pin that determines the maximum on - time when the fet is in linear current limit, and controls the pwm duty cycle for pulsed load capacitor charging. a cap acitor should be attached to this pin. when the fet is in current limit, a 19 a current source charges the external capacitor. if the fet is still in current limit when the timer capacitor reaches 2.5 v, the gate driver is turned off and a 1 a discharge current sink is turned on. the gate remains low until the timer capacitor is reduced to 0.5 v. at this point, the gate pin is turned on again. if the fet goes back into current limit, the timer recharging starts again. the pwm duty cycle is set at 6% defau lt level by the size of these two current sources. adding a resistor from timer to v ee decreases the duty cycle. adding a resistor from timer to v in increases the duty cycle. in addition, a current proportional to the current into the drain pin is added t o the charging current. the additional current varies linearly with drain voltage. this reduce s the maximum on - time and the percentage pwm duty cycle when there is a large voltage across the fet.
adm1073 data sheet rev. b | page 16 of 24 drain analog input fed by a resistor connected to the drai n of the fet. this pin is clamped to go no higher than 4 v with respect to v ee. below this level, the voltage on the pin is monitored so that, if it falls below 2 v, the pwrgd output can be set. above the 4 v level, the current into the pin is detected and used to modu late the maximum on - time for the linear fet driver. this is done by summing a proportion of the drain input current with the charging current for the timer timing cap acitor , thereby reducing the allowable on - time. pwrgd output to indicate when the load capacitor is fully charged. this is an open collector output with internal pull - up to v in . when a normal startup is initiated, the pwrgd output is latched low when the drain pi n falls below 2 v. the latch is reset, if either the input supply goes out of range or a current limit time - out event occurs. the second of these cases ensures that, if a voltage step of greater than 2 v is presented at the input, the p wrgd flag does not go high while the load capacitor is being charged up to the additional voltage. latched output to indicate when the device has completed the maxi - mum number (7) of pwm cycles. this is an open collector output wi th an internal current source pull - up. if this pwm time - out event occurs, the gate pin is latched low and the latched output is set low. this condition can then be reset by either a power cycling event or a low signal to either the shdn input or the restart input. by connecting the latched signal directly to shdn , the device can effec tively be put into a continuous pwm mode. by connecting the latched signal directly to restart , the device can effectively be put in to autoretry mode, with a 5 - second cooling period. splygd output to indicate when the input supply is within the pr o - grammed voltage window. this is an open collector output with an internal pull - up current source. for very large capacitive loads where multiple fets and controllers are required to meet the inrush requirements, this output can be used to drive directly into the uv pin of a second controller. this allows the second fet to start 1 ms after the first one, with the added advantage that the input supply uv detection is done on one controller only. the splygd output is assert ed only when the adm1073 is not in reset mode. restart edge - triggered input. allows the user to remotely command a 5 - second shutdown and restart of the hot swap function, effectively simulating a board removal and replacement. the shutdown funct ion is triggered by a low pulse of at least 5 s at the pin. this pin has an internal pull - up of approximately 6 a, allowing it to be driven by an open collector pull - down output or a push - pull output. the input threshold is 1.5 v. shd n level - triggered input. allows the user to command a shutdown of the hot swap function. when this input is set low, the gate output is switched to v ee to turn the fet off. this pin has an internal pull - up of approximately 6 a, allowing it to be drive n by an open collector pull - down output or a push - pull output. the input threshold is 1.5 v. undervoltage/overvol tage detection the adm1073 incorporates dual pin undervoltage and overvoltage detection, with a programmable operating voltage window. when the voltage on the uv pin falls below the uv falling threshold or the voltage on the ov pin rises above the ov rising threshold, a fault signal is generated that disables the linear current regulator and results in the gate pin being pulled low. the voltage f ault signal is time filtered so that faults of a duration less than the uv glitch filter time (0.6 ms) and ov glitch filter time (5 s) do not force the gate drive low. the filter oper ates only on the faulting edge, that is, on a high - to - low transition on the undervoltage monitor and on a low - to - high transi tion on the overvoltage monitor . 04488-033 1.93v 868mv unde r vo lt age detec t or ove r vo lt age detec t or adm1073 fet drive enable sp l ygd ? 48v rtn ? 48v in r 4 r 3 r 2 r 1 ov uv v in figure 33 . undervoltage and overvoltage circuitry (standard 4 - resistor configuration) the operating voltage window is determined by select ing t he resistor ratios r 1/r2 and r3/r4 . these resistor networks form two resistor dividers that generate the voltages at the uv and ov pin s, which are proportional to the supply voltage. by choosing these ratios carefully, the user can program the adm1073 to a pply the supply voltage to the load only when it is within specific thresholds. note that 1% tolerance resistors should always be used to maintain the accuracy of the pro - grammed thresholds.
data sheet adm1073 rev. b | page 17 of 24 uv (undervoltage) the voltage on the uv pin is compared to an in ternal 0.868 v reference. for the implementation in figure 33 , t he undervolt - age level is then set as v uv = 0.868 ( r1 + r2 )/ r2 if the uv pin voltage is less than 0.868 v and the comparator trips, an internal 5 a current sink is turned on. this pulls the uv voltage down by v uvhyst(pin) = 5 a r1 r 2 /( r1 + r2 ) at the uv pin , or by v uvhyst(supply) = 5 a r1 at the supply . in this manner, the user can program the value of the voltage hysteresis by varying the parallel impedance of th e resistor divider. the uv comparator has an internal 0.6 ms time delay to prevent nuisance shutdowns under noisy supply conditions. ov (overvoltage) the voltage on the uv pin is compared to an internal 1.93 v reference. for the implementation in figure 33 , t he overvoltage level is then set as v ov = 1.93 ( r3 + r4 )/ r 4 if the ov pin voltage exceeds 1.93 v and the comparator trips, an internal 5 a current source is turned on. this pulls the ov voltage up by v ovhyst(pin) = 5 a r3 r4 /( r3 + r4 ) at the ov pin , or by v ovhyst(supply) = 5 a r3 at the supply . in this manner, the user can program the value of the voltage hysteresis by varying the parallel impedance of the resistor divider. the ov comparator has an internal 5 s time delay. if the voltage o n uv or ov goes out of range (below 0.868 v on uv or above 1.93v on ov), gate is pulled low. if the supply subsequently reenters the operating voltage window, the adm1073 restores the gate drive. hysteresis must be considered when reentering the operating window, that is, v uv must increase above 0.868 v + v uvhyst(supply) when recovering from an undervoltage fault, and v ov must drop below 1.93 v ? v ovhyst(supply) when recovering from an overvoltage fault for gate to be restored. alternative uv and ov c o nfigurations a 2 - resistor or a 3 - resistor implementation can also be used to set the uv and ov levels (see figure 34 and figure 35 ). 04488-034 adm1073 ? 48v rtn ? 48v in r 2 r 1 ov uv figure 34 . 2 - resistor uv/ov implementation 04488-035 adm1073 ? 48v rtn ? 48v in r 3 r 1 r 2 ov uv figure 35 . 3 - resistor uv/ov implementation
adm1073 data sheet rev. b | page 18 of 24 functionality and timing live insertion the timing waveforms associated with the live insertion of a plug-in board using the adm1073 are shown in figure 36. the long connector pins are the first to make connection, and the gnd ? v ee potential climbs to 48 v. as this voltage is applied, the voltage at the v in pin ramps to a constant 12.3 v and is held at this level with the shunt resistor and external resistor combination at the v in pin. in this case, the connection pins are staggered so that the r1/r2 and r3/r4 resistor dividers are the last to connect to the backplane. this means that v uv and v ov begin to ramp after the other pins connect. note that staggered connector pins are optional, because an internal time filter is included on the uv pin. when v uv crosses the undervoltage rising threshold, it is now inside the operating voltage window and the ?48 v supply must be applied to the load. the splygd output is asserted and after a time delay, t por , the adm1073 begins to ramp up the gate drive. when the voltage on the sense pin reaches 100 mv (the analog current limit level), the gate drive is held constant. when the board capacitance is fully charged, the sense voltage begins to drop below the analog current limit voltage and the gate voltage is free to ramp up further. the gate voltage eventually climbs to its maximum value of 12.3 v and the pwrgd output is asserted. figure 37 shows some typical startup waveforms. t por v lko v uvr ?48v rtn ? vee v in v uv gate sense v out splygd pwrgd 0 4488-036 figure 36. timing waveforms associated with a live insertion event 04488-037 figure 37. typical startup sequence (ch1 = gate; ch2 = sense; ch3 = pwrgd ; ch4 = splygd ) overvoltage and undervoltage faults the waveforms for an overvoltage glitch are shown in figure 38. when v ov glitches above the overvoltage threshold of 1.93 v, an overvoltage condition is detected and the gate voltage is pulled low. v ov begins to drop back toward the operating voltage window, and the gate drive is restored when the overvoltage falling threshold (1.93 v minus preset ov hysteresis level) is reached. figure 38 illustrates the adm1073s reactions to an overvoltage condition. 04488-038 figure 38. timing waveforms associated with an overvoltage fault (ch1 = gate; ch2 = ov; ch3 = pwrgd ; ch 4 = splygd )
data sheet adm1073 rev. b | page 19 of 24 an undervoltage glitch is dealt with in a similar way. when v uv falls below the undervoltage threshold of 0.868 v, t h e g at e voltage is pulled low. v uv begins to rise back toward the operating voltage window, and the gate drive is restored when the undervoltage rising threshold (0.868 v plus preset uv hysteresis level) is reached. figure 39 illustrates the adm1073s oper ation in an undervoltage situation. 04488-039 figure 39 . timing waveforms associ ated with an undervoltage fault (ch1 = gate; ch2 = uv; ch3 = pwrgd ; ch4 = splygd ) soft start the adm1073 offers a variable soft start feature. the value of the capacitor on the ss pin sets the ramp rate of the inrush current profile at startup. figure 40 to figure 42 show different inrush current ramp rates for three ss capacitors. 04488-040 figure 40 . soft start profile with a 0.1 nf capacitor (ch1 = gate; ch2 = sense) 04488-041 figure 41 . soft start profile with a 1.5 nf capacitor (ch1 = gate; ch2 = sense) 04488-042 fi gure 42 . soft start profile with an 8.2 nf capacitor (ch1 = gate; ch2 = sense)
adm1073 data sheet rev. b | page 20 of 24 current faults some timing waveforms associated with overcurrent faults are shown in the following figures. figure 43 shows how a perma - nent current fault is dealt with after startup. splygd going low indicates when the supply voltage is good. because the output is shorted, the sense voltage immediately rises through the 90 mv circuit breaker threshold , and the fault timer is started. the linear current control loop then goes into regulation at v sense = 100 mv , accurately limiting the load current at the preset level. the limited consecutive retry scheme pwms the gate p in seven times. when the seventh ret ry occurs, the permanent fault is deemed permanent and the part latches off. the latched output asserts at this time. power must now be cycled to restart the device. this can be achieved via a manual card reseating event (which cycle s the power) or with an external restart or shdn signal. 04488-043 figure 43 . timing waveforms associated with a current fault at startup, using limited consecutive retry (ch1 = gate; ch2 = se nse; ch3 = splygd ; ch4 = latched ) note that the latched output can also be tied back to the restart input, giving an infinite retry during current fault with a 5 - s econd cool - down period after every seven retries. the waveforms for this event are similar to th ose in figure 43 , but repeat s every five seconds. figure 44 shows the behavior of adm1073 when a temporary c urrent fault occurs followed by a permanent current fault. when the first overcurrent fault occurs, the first 97.5 mv spike on the sense line can be seen. the adm1073 retries a number of times, and during the fifth t off time this current fault corrects its elf. after this time period, a no - fault condition is detected and the limited consecutive counter is reset. gate is reasserted. when the overcurrent fault returns permanently, the limited consecutive retry counter detects seven consecutive faults and the part latches off. in this way, the adm1073 prevents nuisance shutdowns caused by transient shorts of a programmable duration (typically ~0.6 s, set via timer, as follows ), but provides latched shutdown protection from permanently shorted loads. 04488-044 figure 44 . timing waveforms associated with a temporary current fault followed by a permanent current fault (ch1 = gate; ch2 = sense) figure 45 shows the behavior of the timer pin during a retry cycle. different c urrent sources are switched in during the on - time (timer ramping up) and off - times (timer ramping down). this can be seen in the varying ramp - up and ramp - down rates of timer below. the default ratio of t on to t off is 6%. this ratio can be reduced with a re sistor from timer to v ee or increased with a resistor from timer to v in . the total retry period can be extended or reduced by changing the value of the timer capacitor. 04488-045 figure 45 . timing wavef orms during a retry cycle for c timer = 0.82 nf (ch1 = gate; ch2 = sense; ch3 = timer)
data sheet adm1073 rev. b | page 21 of 24 logic inputs figure 46 shows assertion of the level-triggered shdn signal for 150 ms, causing the adm1073 to shut down for this duration. 04488-046 figure 46. timing waveforms associated with a reset event (ch1 = gate; ch2 = shdn ; ch3 = pwrgd ; ch4 = splygd ) figure 47 shows the assertion of the edge-triggered restart signal, causing the adm1073 to shut down for approximately five seconds before restarting automatically. 04488-047 figure 47. timing waveforms associated with a restart event (ch1 = gate; ch2 = restart ; ch3 = pwrgd ; ch4 = splygd ) kelvin sense resistor connection when using a low-value sense resistor for high current measurement, the problem of parasitic series resistance can arise. the lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. this problem can be avoided by using a kelvin sense connection. this type of connection separates the current path through the resistor and the voltage drop across the resistor. figure 48 shows the correct way to connect the sense resistor between the sense and v ee pins of the adm1073. kelvin sense traces sense v ee adm1073 current flow from load current flow to ?48v backplane sense resistor 04488-048 figure 48. kelvin sensing with the adm1073
adm1073 data sheet rev. b | page 22 of 24 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 49. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADM1073ARUZ ?40c to +85c 14-lead tssop ru-14 ADM1073ARUZ-reel ?40c to +85c 14-lead tssop ru-14 ADM1073ARUZ-reel7 ?40c to +85c 14-lead tssop ru-14 eval-adm1073mebz micro evaluation board 1 z = rohs compliant part.
data sheet adm1073 rev. b | page 23 of 24 notes
adm1073 data sheet rev. b | page 24 of 24 notes ? 2004 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04488 C0 C7 / 13 ( b )

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